Fault Classification for Self-checking Circuits Implemented in Fpga

This paper focuses on a fault classification problem for concurrent error detection circuits based on error detecting codes. The proposed fault classification differs from the common classification, where the faults are divided into two groups – the testable faults and the untestable faults. The faults are divided into four groups in our approach, by their impact to fault secure and self-testing properties. Our fault simulation software has been used to evaluate the proposed fault classification on real benchmarks. The benchmarks were implemented in a FPGA, and stuck-at-1 and stuck-at-0 fault model has been considered.